1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to the structure of a plug in the semiconductor device and a method of forming the plug.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory) device includes an array of memory cells for storing therein data. Each memory cell includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed on the surface portion of a semiconductor substrate and a cell capacitor overlying the semiconductor substrate and connected to the MISFET through a plug. The memory cell accumulates charge in the cell capacitor via the MISFET to thereby store therein data.
In manufacture of the DRAM device, the MISFETs are first formed on the surface portion of the semiconductor substrate and then an interlayer dielectric film is deposited to cover the semiconductor substrate and MISFETs. Contact holes are then formed to penetrate the interlayer dielectric film to expose therethrough source/drain diffused regions of the MISFETs. Thereafter, a conductive material or materials are embedded within the contact holes to form therein contact plugs. Further, bit lines and cell capacitors are formed to overlie the interlayer dielectric film, and connected to the contact plugs directly or through via-plugs. A plurality of interlayer dielectric films as well as a plurality of conducting layers including the contact plugs and via-plugs are stacked one on another to form a multilayer interconnection structure.
In recent years, to meet the demand on higher integration of DRAM devices, the area in which the memory cell occupies on the semiconductor substrate has been drastically reduced, with the result that the space between adjacent plugs has been significantly reduced. Therefore, the positional accuracy of the plugs has been improved and the diameter of the plugs is reduced in the recent DRAM devices, to thereby prevent a short-circuit failure from occurring between the plugs. Meanwhile, in a dry etching process for forming the contact holes and via-holes (hereinafter referred to as collectively via-holes), it is noted that the etching performance is degraded if the depth of via-holes being etched is increased, with the result that the plugs have a smaller diameter at the position of a larger depth, whereby the via-holes have a tapered structure. The tapered via-plugs decrease the contact area between the tapered via-plugs and the underlying plugs, thereby causing the problem of increase in the contact resistance therebetween.
To solve the aforementioned problem, Patent Publication JP-1998-270555A1 describes a technique for enlarging the contact area between the via-plugs and the underlying conductive layer by increasing the diameter in the vicinity of the bottom of the via-holes. In the technique of the JP-1998-270555A1, an interlayer dielectric film receiving therein via-plugs has a two-layer structure, wherein the etch rate of the lower interlayer dielectric layer is higher than that of the upper interlayer dielectric layer. Via-holes penetrating the interlayer dielectric layers are formed by a dry etching process, and then the lower interlayer dielectric layer is selectively etched by a wet etching process to enlarge the diameter in the vicinity of the bottom of the via-holes.
The technique described in JP-1998-270555A1 is such that both the upper and lower interlayer dielectric layers are made of silicon oxide doped with impurities. The impurity concentration of the lower interlayer dielectric layer is higher than that of the upper interlayer dielectric layer, thereby allowing the etch rate of the lower interlayer dielectric layer to be higher than that of the upper interlayer dielectric layer.
The contact area between the plugs and the underlying conductive layer is enlarged by increasing the diameter in the vicinity of the bottom of the via-holes so as to suppress an increase in the contact resistance between the plugs and the underlying conductive layer. However, the method described in the above patent publication has a problem in that the diameter in the vicinity of the bottom the via-holes is difficult to control during the wet etching process performed for increasing the diameter. An excessively larger diameter of the via-plugs in the vicinity of the bottom thereof may cause a short-circuit failure between adjacent interconnections in the underlying conductive layer.